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KAD5612P
Data Sheet December 5, 2008 FN6803.0
Dual 12-Bit, 250/210/170/125MSPS A/D Converter
The KAD5612P is a family of low-power, high-performance, dual-channel 12-bit, analog-to-digital converters. Designed with FemtoChargeTM technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The KAD5612P-25 is the fastest member of this pin-compatible family, which also features sample rates of 210MSPS (KAD5612P-21), 170MSPS (KAD5612P-17) and 125MSPS (KAD5612P-12). A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of gain, skew and offset matching between the two converter cores. Digital output data is presented in selectable LVDS or CMOS formats. The KAD5612P is available in a 72-contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40C to +85C).
Features
* Programmable Gain, Offset and Skew control * 1.3GHz Analog Input Bandwidth * 60fs Clock Jitter * Over-Range Indicator * Selectable Clock Divider: /1, /2 or /4 * Clock Phase Selection * Nap and Sleep Modes * Two's Complement, Gray Code or Binary Data Format * DDR LVDS-Compatible or LVCMOS Outputs * Programmable Built-in Test Patterns * Single-Supply 1.8V Operation * Pb-Free (RoHS Compliant)
Applications
* Power Amplifier Linearization * Radar and Satellite Antenna Array Processing * Broadband Communications * High-Performance Data Acquisition
CLKDIV
CLKP CLKN
OVDD
AVDD
Clock Generation
CLKOUTP CLKOUTN
* Communications Test Equipment * WiMAX and Microwave Receivers
Key Specifications
AINP SHA AINN 12-bit 250MSPS ADC D[11:0]P D[11:0]N ORP ORN
* SNR = 65.1dBFS for fIN = 124MHz (-1dBFS) * SFDR = 80dBc for fIN = 124MHz (-1dBFS) * Power consumption - 405mW @ 250MSPS - 324mW @ 125MSPS
VREF
VCM
Digital Error Correction
OUTFMT BINP SHA BINN 12-bit 250MSPS ADC
VREF
OUTMODE
Pin-Compatible Family
MODEL KAD5612P-25 RESOLUTION 12 12 12 12 10 10 10 10 SPEED (MSPS) 250 210 170 125 250 210 170 125
1.25V
+ -
SPI Control
CSB SCLK SDIO SDO
NAPSLP
RESET
OVSS
AVSS
KAD5612P-21 KAD5612P-17 KAD5612P-12 KAD5610P-25 KAD5610P-21 KAD5610P-17 KAD5610P-12
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
KAD5612P Ordering Information
PART NUMBER (Note) KAD5612P-25Q72 KAD5612P-21Q72 KAD5612P-17Q72 KAD5612P-12Q72 SPEED (MSPS) 250 210 170 125 TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 72 Ld QFN 72 Ld QFN 72 Ld QFN 72 Ld QFN PKG. DWG. # L72.10X10D L72.10X10D L72.10X10D L72.10X10D
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN6803.0 December 5, 2008
KAD5612P Table of Contents
Absolute Maximum Ratings ......................................... 4 Thermal Information...................................................... 4 Electrical Specifications ............................................... 4 Digital Specifications .................................................... 6 Timing Diagrams ........................................................... 6 Switching Specifications .............................................. 7 Thermal Impedance....................................................... 7 ESD ................................................................................. 7 Pinout/Package Information......................................... 8 Pin Descriptions.......................................................... 8 Pinout ......................................................................... 9 Typical Performance Curves ........................................ 10 Theory of Operation ...................................................... 13 Functional Description ................................................ Power-On Calibration ................................................. User-Initiated Reset.................................................... Analog Input ............................................................... Clock Input ................................................................. Jitter............................................................................ Voltage Reference...................................................... Digital Outputs ............................................................ Over Range Indicator ................................................. Power Dissipation....................................................... Nap/Sleep................................................................... Data Format ............................................................... 13 13 14 14 15 16 16 16 16 16 16 17 Serial Peripheral Interface ........................................... 18 SPI Physical Interface................................................ SPI Configuration....................................................... Device Information ..................................................... Indexed Device Configuration/Control ....................... Global Device Configuration/Control.......................... Device Test ................................................................ SPI Memory Map ....................................................... 18 19 20 20 21 22 23
Equivalent Circuits ....................................................... 24 Layout Considerations................................................. 25 Split Ground and Power Planes................................. Clock Input Considerations ........................................ Exposed Paddle......................................................... Bypass and Filtering .................................................. LVDS Outputs ............................................................ LVCMOS Outputs ...................................................... Unused Inputs............................................................ 25 25 25 25 25 25 25
Definitions ..................................................................... 25 Revision History ........................................................... 26 Package Outline Drawing............................................. 27 L72.10x10D................................................................ 27
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FN6803.0 December 5, 2008
KAD5612P
Absolute Maximum Ratings
AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Information
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40C to +85C (typical specifications at +25C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). KAD5612P-25 PARAMETER SYMBOL CONDITIONS MIN TYP KAD5612P-21 TYP KAD5612P-17 TYP KAD5612P-12 TYP MAX UNITS
MAX MIN
MAX MIN
MAX MIN
DC SPECIFICATIONS (Note 1) Analog Input Full-Scale Analog Input Range Input Resistance Input Capacitance Full Scale Range Temp. Drift Input Offset Voltage Gain Error Common-Mode Output Voltage Power Requirements 1.8V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 1.8V Digital Supply Current (Note 1) Power Supply Rejection Ratio Power Dissipation Normal Mode Nap Mode Sleep Mode PD PD PD 3mA LVDS 405 134 14 434 146 16 382 129 13 411 142 16 357 124 7 386 138 15 324 118 12 353 131 13 mW mW mW AVDD OVDD IAVDD IOVDD PSRR 3mA LVDS 30MHz, 200mVP-P signal on AVDD 1.7 1.7 1.8 1.8 157 68 -36 1.9 1.9 165 76 1.7 1.7 1.8 1.8 146 66 -36 1.9 1.9 154 74 1.7 1.7 1.8 1.8 134 64 -36 1.9 1.9 142 72 1.7 1.7 1.8 1.8 118 62 -36 1.9 1.9 126 70 V V mA mA dB VFS RIN CIN AVTC VOS EG VCM Differential Differential Differential Full Temp -10 1.42 1.48 1000 1.8 90 2 2 0.535 10 -10 1.56 1.42 1.48 1000 1.8 90 2 2 0.535 10 -10 1.56 1.42 1.48 1000 1.8 90 2 2 0.535 10 -10 1.56 1.42 1.48 1000 1.8 90 2 2 0.535 10 1.56 VP-P pF ppm/C mV % V
AC SPECIFICATIONS (Note 2) Differential Nonlinearity Integral Nonlinearity Minimum Conversion Rate (Note 3) Maximum Conversion Rate DNL INL fS MIN fS MAX 250 -1 0.7 1.6 40 210 -1 0.7 1.6 40 170 -1 0.7 1.6 40 125 -1 0.7 1.6 40 LSB LSB MSPS MSPS
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FN6803.0 December 5, 2008
KAD5612P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40C to +85C (typical specifications at +25C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) KAD5612P-25 PARAMETER Signal-to-Noise Ratio (Note 2) SYMBOL SNR CONDITIONS fIN = 10MHz fIN = 70MHz fIN = 105MHz fIN = 230MHz fIN = 400MHz fIN = 995MHz Signal-to-Noise and Distortion (Note 2) SINAD fIN = 10MHz fIN = 70MHz fIN = 105MHz fIN = 230MHz fIN = 400MHz fIN = 995MHz Effective Number of Bits (Note 2) ENOB fIN = 10MHz fIN = 70MHz fIN = 105MHz fIN = 230MHz fIN = 400MHz fIN = 995MHz Spurious-Free Dynamic Range (Note 2) SFDR fIN = 10MHz fIN = 70MHz fIN = 105MHz fIN = 230MHz fIN = 400MHz fIN = 995MHz Intermodulation Distortion (Note 2) Channel to Channel Isolation Word Error Rate Full Power Bandwidth NOTES: 1. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 2. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to "Power-On Calibration" on page 13 and "User-Initiated Reset" on page 14 for more details. 3. The DLL Range setting must be changed for low speed operation. See "Serial Peripheral Interface" on page 18 for more detail. WER FPBW IMD fIN = 70MHz fIN = 170MHz fIN = 10MHz fIN = 124MHz 70 10 62 62.5 MIN TYP 65.2 65.1 65.1 64.8 64.2 61.4 64 64 63.7 63.5 62.2 53.9 10.3 10.3 10.3 10.3 10 8.7 84 84 80 77 71 57 -90.5 -86 90 90 10-12 1.3 90 90 10-12 1.3 90 90 10-12 1.3 70 84 83 80 76 70 85 82 80 77 70 10.2 10.6 10.6 10.5 10.5 10.3 10.7 10.7 10.6 10.6 10.3 63 65.5 65.7 65.2 65.2 63.7 66 65.9 65.7 65.6 64 63.5 KAD5612P-21 TYP 65.8 65.7 65.6 65.7 64.2 KAD5612P-17 TYP 66.2 66.2 66 66.1 64.5 KAD5612P-12 TYP 66.7 66.6 66.4 66.3 64.7 60.7 66.4 66.3 66 65.8 63.7 53 10.7 10.7 10.7 10.6 10.3 8.5 85 83 80 79 76 54 -96.5 -93 90 90 10-12 1.3 GHz MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBFS dBFS dB dB
MAX MIN
MAX MIN
MAX MIN
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FN6803.0 December 5, 2008
KAD5612P
Digital Specifications
PARAMETER INPUTS Input Current High (RESETN) Input Current Low (RESETN) Input Current High (OUTMODE, NAP/SLP, CLKDIV, OUTFMT) Input Current Low (OUTMODE, NAP/SLP, CLKDIV, OUTFMT) Input Capacitance LVDS OUTPUTS Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time CMOS OUTPUTS Voltage Output High Voltage Output Low Output Rise Time Output Fall Time VOH VOL tR tF IOH = -500A IOL = 1mA OVDD - 0.3 OVDD - 0.1 0.1 1.8 1.4 0.3 V V ns ns VT VOS tR tF 3mA Mode 3mA Mode 950 620 965 500 500 980 mVP-P mV ps ps IIH IIL IIH IIL CDI VIN = 1.8V VIN = 0V 0 -25 15 -40 1 -12 25 25 3 10 -5 40 -15 A A A A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
Timing Diagrams
Sample N INP
Sample N INP
IN N tA C LKN CLKP tC PD C LKOUTN C LKOUTP tDC D[11:0]P D[11:0]N t PD
A Data N-L B Data N -L A Data N-L+1 B Da ta N-L+1 A Data N-L+2 B Data N-L+2 AD a ta N
INN tA CLKN CLKP
Latency = L Cycles
tC PD CLKOUT t DC tPD D[11:0]
A Data N-L BD a ta N-L
Latency = L Cycles
A Data N-L+1
B Data N+ -L 1
A Data N-L+2
BD a ta NL - +2
A Data N
FIGURE 1. LVDS TIMING DIAGRAM--DDR
FIGURE 2. CMOS TIMING DIAGRAM--DDR
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FN6803.0 December 5, 2008
KAD5612P Switching Specifications
PARAMETER ADC Aperture Delay RMS Aperture Jitter Output Clock to Data Propagation Delay, LVDS Mode Output Clock to Data Propagation Delay, CMOS Mode Latency (Pipeline Delay) Overvoltage Recovery SPI INTERFACE (Notes 4, 5) SCLK Period Write Operation Read Operation SCLK Duty Cycle (tHI/tCLK or tLO/tCLK) SCLK to CSB Setup Time SCLK to CSB Hold Time SCLK to Data Setup Time SCLK to Data Hold Time NOTES: 4. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. 5. The SPI may operate asynchronously with respect to the ADC sample clock. Read or Write Read or Write Read or Write Read or Write Read or Write tS tH tDS tDH
t CLK
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
tA jA Rising Edge Falling Edge Rising Edge Falling Edge tDC tDC tDC tDC L tOVR -260 -160 -220 -310
375 60 -50 10 -10 -90 7.5 1 120 230 200 110
ps fs ps ps ps ps cycles cycles
64 264 25 -4 -12 -4 -12 50 75
ns ns % ns ns ns ns
tCLK
Thermal Impedance
PARAMETER Junction to Ambient (Note 6) NOTE: 6. Paddle soldered to ground plane. SYMBOL JA TYP 27 UNIT C/W
ESD
Electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated circuit. Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive products. Contact Intersil for the specific ESD sensitivity rating of this product.
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FN6803.0 December 5, 2008
KAD5612P Pinout/Package Information
Pin Descriptions
PIN NUMBER 1, 6, 19, 24, 71 2-5, 17, 18, 28-31 7, 10-12, 72 8, 9 13, 14 15 16 20, 21 22 23 25 26, 45, 55, 65 27, 36, 56 32, 33 34, 35 37, 38 39, 40 41, 42 43, 44 46 47, 48 49, 50 51, 52 53, 54 57, 58 59, 60 61, 62 63, 64 66 67 68 69 70 Exposed Paddle LVDS [LVCMOS] NAME AVDD DNC AVSS BINP, BINN AINN, AINP VCM CLKDIV CLKP, CLKN OUTMODE NAPSLP RESETN OVSS OVDD D0N, D0P [NC, D0] D1N, D1P [NC, D1] D2N, D2P [NC, D2] D3N, D3P [NC, D3] D4N, D4P [NC, D4] D5N, D5P [NC, D5] RLVDS CLKOUTN, CLKOUTP [NC, CLKOUT] D6N, D6P [NC, D6] D7N, D7P [NC, D7] D8N, D8P [NC, D8] D9N, D9P [NC, D9] D10N, D10P [NC, D10] D11N, D11P [NC, D11] ORN, ORP [NC, OR] SDO CSB SCLK SDIO OUTFMT AVSS 1.8V Analog Supply Do Not Connect Analog Ground B-Channel Analog Input Positive, Negative A-Channel Analog Input Negative, Positive Common Mode Output Clock Divider Control Clock Input True, Complement Output Mode (LVDS, LVCMOS) Power Control (Nap, Sleep modes) Power On Reset (Active Low) Output Ground 1.8V Output Supply LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0] LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1] LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2] LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3] LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4] LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5] LVDS Bias Resistor (connect to OVSS with a 10k, 1% resistor) LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT] LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6] LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7] LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8] LVDS Bit 9 Output Complement, True [NC, LVCMOS Bit 9] LVDS Bit 10 Output Complement, True [NC, LVCMOS Bit 10] LVDS Bit 11(MSB) Output Complement, True [NC, LVCMOS Bit 11] LVDS Over Range Complement, True [NC, LVCMOS Over Range] SPI Serial Data Output (4.7k pull-up to OVDD is required) SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Output Data Format (Two's Comp., Gray Code, Offset Binary) Analog Ground LVDS [LVCMOS] FUNCTION
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
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FN6803.0 December 5, 2008
KAD5612P
Pinout
KAD5612 (72 LD QFN) TOP VIEW
AVDD DNC DNC DNC DNC AVDD AVSS BINP BINN AVSS AVSS AVSS AINN AINP VCM CLKDIV DNC DNC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
AVSS AVDD OUTFMT SDIO SCLK CSB SDO OVSS ORP ORN D11P D11N D10P D10N D9P D9N OVDD OVSS
KAD5612
72 QFN
Top View Not to Scale
D8P D8N D7P D7N D6P D6N CLKOUTP CLKOUTN RLVDS OVSS D5P D5N D4P D4N D3P D3N D2P D2N
9
AVDD CLKP CLKN OUTMODE NAPSLP AVDD RESETN OVSS OVDD DNC DNC DNC DNC D0N D0P D1N D1P OVDD
FIGURE 3. PIN CONFIGURATION
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FN6803.0 December 5, 2008
KAD5612P Typical Performance Curves
90
HD2 & HD3 MAGNITUDE (dBc)
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade).
-50
SNR (dBFS) & SFDR (dBc)
85 SFDR @ 125MSPS 80 SFDR @ 250MSPS 75 70 65 60 SNR @ 250MSPS 55 50 0 200 400 600 800 1000 INPUT FREQUENCY (MHz) SNR @ 125MSPS
-55 -60 -65 HD3 @ 125MSPS -70 -75 -80 -85 HD2 @ 250MSPS -90 0 200 400 600 800 1000 INPUT FREQUENCY (MHz) HD2 @ 125MSPS HD3 @ 250MSPS
FIGURE 4. SNR AND SFDR vs fIN
FIGURE 5. HD2 AND HD3 vs fIN
100 90 80 SNR & SFDR 70 60 50 40 30 20 10 0 -70 -60 -50 SFDR (dBc) SNRFS (dBFS)
-20 SFDRFS (dBFS) HD2 & HD3 MAGNITUDE -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -40 -30 -20 -10 0 -70 -60 -50 -40 -30 -20 -10 0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) HD3 (dBFS) HD2 (dBFS) HD3 (dBc) HD2 (dBc)
SNR (dBc)
FIGURE 6. SNR AND SFDR vs AIN
FIGURE 7. HD2 AND HD3 vs AIN
95 SNR (dBFS) & SFDR (dBc) 90 SFDR 85 80 75 70 65 60 40 70 100 130 160 190 220 250 SAMPLE RATE (MSPS) SNR HD2 & HD3 MAGNITUDE (dBc)
-60 -70 HD3 -80 -90 -100 HD2 -110 -120 40 70 100 130 160 190 220 250 SAMPLE RATE (MSPS)
FIGURE 8. SNR AND SFDR vs fSAMPLE
FIGURE 9. HD2 AND HD3 vs fSAMPLE
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FN6803.0 December 5, 2008
KAD5612P Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued)
1 .5 1 0 .5 0 -0 .5 -1 -1 .5
450 400 TOTAL POWER (mW) 350
250 200 150 100 50 0 40 70 100 130 160 190 220 250 SAMPLE RATE (MSPS)
D N L (L SBs)
300
0
51 2
1 02 4
1 5 36
20 48 2 56 0 CO DE
3 0 72
35 8 4
4 09 6
FIGURE 10. POWER vs fSAMPLE IN 3mA LVDS MODE
FIGURE 11. DIFFERENTIAL NONLINEARITY
2 SNR (dBFS) & SFDR (dBc) 1 .5 1 IN L (LS Bs) 0 .5 0 -0 .5 -1 -1 .5 -2 0 51 2 1 02 4 1 5 36 20 48 2 56 0 CO DE 3 0 72 35 8 4 4 09 6
90 85 SFDR 80 75 70 SNR 65 60 55 50 300
400
500
600
700
800
INPUT COMMON MODE (mV)
FIGURE 12. INTEGRAL NONLINEARITY
FIGURE 13. SNR AND SFDR vs VCM
7 0 00 0 6 5 00 0 6 0 00 0 5 5 00 0 5 0 00 0 4 5 00 0 4 0 00 0 3 5 00 0 3 0 00 0 2 5 00 0 2 0 00 0 1 5 00 0 1 0 00 0 5 00 0 0 20 48 20 4 9 20 5 0 2 05 1 2 05 2 20 5 3 2 05 4 2 05 5 2 05 6 2 05 7 C OD E
0 -20 A M PLIT U D E (d BFS ) -40 -60 -80 -1 00 -1 20
A in = -1.1 dBFS S NR = 65. 1 d BFS S FDR = 81. 3 dBc S INA D = 6 5.0 dB FS
N UM BER O F H IT S
0
20
40 60 80 FR EQ U EN CY ( M Hz)
1 00
1 20
FIGURE 14. NOISE HISTOGRAM
FIGURE 15. SINGLE-TONE SPECTRUM @ 10MHz
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FN6803.0 December 5, 2008
KAD5612P Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued)
0
Ain = -1. 0 dBFS SNR = 6 4. 9 d B FS SFDR = 83. 2 d B c SINAD = 64.8 dBFS
0 -20 A M PLIT U D E (d BF S ) -40 -60 -80 -1 00 -1 20
-20 A M PLIT U D E (d BF S ) -40 -60 -80 -1 00 -1 20
A in = -1.1 dBFS S NR = 64. 8 d BFS S FDR = 80. 1 dBc S INA D = 6 4.6 dB FS
0
20
40 60 80 FR EQ U EN CY ( M Hz)
1 00
1 20
0
20
40 60 80 FR EQ U EN CY ( M Hz)
1 00
1 20
FIGURE 16. SINGLE-TONE SPECTRUM @ 105MHz
FIGURE 17. SINGLE-TONE SPECTRUM @ 190MHz
0 -20 A M PLIT U D E (d BFS ) -40 -60 -80 -1 00 -1 20
A in = -1.1 dBFS S NR = 64. 0 d BFS S FDR = 73. 5 dBc S INA D = 6 3.6 dB FS
0 -20 A M PLITU D E (d BF S ) -40 -60 -80 -1 00 -1 20
A in = -1.0 dBFS S NR = 61. 7 d BFS S FDR = 52. 0 dBc S INA D = 5 1.8 dB FS
0
20
40 60 80 FR EQ U EN CY ( M Hz)
1 00
1 20
0
20
40 60 80 FR EQ U EN CY ( M Hz)
1 00
1 20
FIGURE 18. SINGLE-TONE SPECTRUM @ 495MHz
FIGURE 19. SINGLE-TONE SPECTRUM @ 995MHz
0 -20 A M PLITU D E (d BF S ) -40 -60 -80 -1 00 -1 20
IMD = -9 0. 4dBFS
0 -20 A M PLIT U D E (d BFS ) -40 -60 -80 -1 00 -1 20
IMD = -8 3. 5dBFS
0
20
40 60 80 FR EQ U EN CY ( M Hz)
1 00
1 20
0
20
40 60 80 FR EQ U EN CY ( M Hz)
1 00
1 20
FIGURE 20. TWO-TONE SPECTRUM @ 70MHz
FIGURE 21. TWO-TONE SPECTRUM @ 170MHz
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FN6803.0 December 5, 2008
KAD5612P Theory of Operation
Functional Description
The KAD5612P is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 22). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. The converter pipeline requires six samples to produce a result. Digital error correction is also applied, resulting in a total latency of seven and one half clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. The device contains two A/D converter cores with carefully matched transfer characteristics. At start-up, each core performs a self-calibration to minimize gain and offset errors. The reset pin (RESETN) is initially set high at power-up and will remain in that state until the calibration is complete. The clock frequency should remain fixed during this time, and no SPI communications should be attempted. Recalibration can be initiated via the SPI port at any time after the initial self-calibration.
Power-On Calibration
The ADC performs a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: * A frequency-stable conversion clock must be applied to the CLKP/CLKN pins * DNC pins (especially 3, 4 and 18) must not be pulled up or down * SDO (pin 66) must be high * RESETN (pin 25) must begin low * SPI communications must not be attempted A user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. The SDO pin requires an external 4.7k pull-up to OVDD. If the SDO pin is pulled low externally during power-up, calibration will not be executed properly. After the power supply has stabilized the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is required, the RESETN pin should be connected to an open-drain driver with a drive strength of less than 0.5mA.
Clock Generation
INP SHA INN
2.5-bit Flash
6-Stage 1.5-bit/stage
3-Stage 1-bit/stage
3-bit Flash
1.25V
+ -
Digital Error Correction
LVDS/LVCMOS Outputs
FIGURE 22. ADC CORE BLOCK DIAGRAM
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FN6803.0 December 5, 2008
KAD5612P
The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 23. The over-range output (OR) is set high once RESETN is pulled low, and remains in that state until calibration is complete. The OR output returns to normal operation at that time, so it is important that the analog input be within the converter's full-scale range to observe the transition. If the input is in an over-range condition the OR pin will stay high, and it will not be possible to detect the end of the calibration cycle. While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is deasserted. At 250MSPS the nominal calibration time is 200ms, while the maximum calibration time is 550ms.
CLKN CLKP Calibration Time RESETN Calibration Begins ORP Calibration Complete CLKOUTP
SFDR CHANGE (dBc) 15 10 5 0 -5 -10 -15 -40 -15 10 35 60 85 TEMPERATURE ( C)
the ADC is calibrated at 25C and temperature is varied over the operating range without recalibrating. The average change in SNR/SFDR is shown, relative to the +25C value.
4 3 SNR CHANGE (dBFS) 2 1 0 -1 -2 -3 -4 -40 -15 10 35 60 85 TEMPERATURE (C)
FIGURE 24. SNR PERFORMANCE vs TEMPERATURE AFTER +25C CALIBRATION
FIGURE 23. CALIBRATION TIMING
User-Initiated Reset
Recalibration of the ADC can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength of less than 0.5mA is recommended. As is the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5612P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the ADC under the environmental conditions at which it will operate. A supply voltage variation of less than 100mV will generally result in an SNR change of less than 0.5dBFS and SFDR change of less than 3dBc. In situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. Reducing the sample rate by less than 75MSPS will typically result in an SNR change of less than 0.5dBFS and an SFDR change of less than 3dBc. Figures 25 and 26 show the effect of temperature on SNR and SFDR performance without recalibration. In each plot
FIGURE 25. SFDR PERFORMANCE vs TEMPERATURE AFTER +25C CALIBRATION
Analog Input
Each ADC core contains a fully differential input (AINP/AINN, BINP/BINN) to the sample and hold amplifier (SHA). The ideal full-scale input voltage is 1.45V, centered at the VCM voltage of 0.535V as shown in Figure 26. Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 27 through 29.
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KAD5612P
1.8
69.8O
348O 25O
1.4 1.0 0.6 0.2 0.725V INP
INN VCM 0.535V
0.22F
100O 217O
CM
KAD5512P
VCM
100O 69.8O 348O 25O
0.1F
49.9O
FIGURE 26. ANALOG INPUT RANGE
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 27 and 28.
ADT1-1WT 1000pF ADT1-1WT
A differential amplifier, as shown in Figure 29, can be used in applications that require dc-coupling. In this configuration the amplifier will typically dominate the achievable SNR and distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 43). Driving these inputs with a high level (up to 1.8VPP on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. The recommended drive circuit is shown in Figure 30. A duty range of 40% to 60% is acceptable. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 to facilitate AC coupling.
200pF TC4-1W
KAD5512P
VCM
0.1F
FIGURE 27. TRANSFORMER INPUT FOR GENERAL PURPOSE APPLICATIONS
ADTL1-12 1000pF 1000pF
ADTL1-12 0.1F KAD5512P
VCM
CLKP 1000pF
200pF
200O
CLKN 200pF
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH IF APPLICATIONS
FIGURE 30. RECOMMENDED CLOCK DRIVE
This dual transformer scheme is used to improve commonmode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5612P is 1000. The SHA design uses a switched capacitor input stage (see Figure 42), which creates current spikes when the sampling capacitance is reconnected to the input voltage. This causes a disturbance at the input which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance.
A selectable 2X frequency divider is provided in series with the clock input. The divider can be used in the 2X mode with a sample clock equal to twice the desired sample rate. This allows the use of the Phase Slip feature, which enables synchronization of multiple ADCs.
TABLE 1. CLKDIV PIN SETTINGS CLKDIV PIN AVSS Float AVDD DIVIDE RATIO 2 1 4
The clock divider can also be controlled through the SPI port, which overrides the CLKDIV pin setting. Details on this are contained in "Serial Peripheral Interface" on page 18.
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KAD5612P
A delay-locked loop (DLL) generates internal clock signals for various stages within the charge pipeline. If the frequency of the input clock changes, the DLL may take up to 52s to regain lock at 250MSPS. The lock time is inversely proportional to the sample rate. Additionally, the drive current for LVDS mode can be set to a nominal 3mA or a power-saving 2mA. The lower current setting can be used in designs where the receiver is in close physical proximity to the ADC. The applicability of this setting is dependent upon the PCB layout, therefore the user should experiment to determine if performance degradation is observed. The output mode and LVDS drive current are selected via the OUTMODE pin as shown in Table 2.
TABLE 2. OUTMODE PIN SETTINGS OUTMODE PIN AVSS Float
tj=0.1p s 90 85 1 4 Bits
Jitter
In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 31.
1 SNR = 20 log 10 ------------------- 2f t
IN J
100 95
(EQ. 1)
MODE LVCMOS LVDS, 3mA LVDS, 2mA
AVDD
SNR - dB
80 75 70 65 60 55 50 1 10 tj=1 0 0p s tj=10p s
tj=1 ps
1 2 Bits
The output mode can also be controlled through the SPI port, which overrides the OUTMODE pin setting. Details on this are contained in "Serial Peripheral Interface" on page 18. An external resistor creates the bias for the LVDS drivers. A 10k, 1% resistor must be connected from the RLVDS pin to OVSS.
10 Bits
10 0
1 0 00
Input Frequency - MHz
Over Range Indicator
The over range (OR) bit is asserted when the output code reaches positive full-scale (e.g. 0xFFF in offset binary mode). The output code does not wrap around during an over range condition. The OR bit is updated at the sample rate.
FIGURE 31. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise. Internal aperture jitter is the uncertainty in the sampling instant shown in Figure 1. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR.
Power Dissipation
The power dissipated by the KAD5612P is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs. SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation changes to a lesser degree in LVDS mode, but is more strongly related to the clock frequency in CMOS mode.
Voltage Reference
A temperature compensated voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each A/D is proportional to the reference voltage. The nominal value of the voltage reference is 1.25V.
Nap/Sleep
Portions of the device may be shut down to save power during times when operation of the ADC is not required. Two power saving modes are available: Nap, and Sleep. Nap mode reduces power dissipation to less than 134mW and recovers to normal operation in approximately 1s. Sleep mode reduces power dissipation to less than 14mW but requires 1ms to recover. All digital outputs (Data, CLKOUT and OR) are placed in a high impedance state during Nap or Sleep. The input clock should remain running and at a fixed frequency during Nap or Sleep. Recovery time from Nap mode will increase if the clock is stopped, since the internal DLL can take up to 52s to regain lock at 250MSPS.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible or CMOS modes. In either case, the data is presented in double data rate (DDR) format with the A and B channel data available on alternating clock edges. When CLKOUT is low channel A data is output, while on the high phase channel B data is presented. Figures 1 and 2 show the timing relationships for LVDS and CMOS modes, respectively.
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By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown in Table 3.
TABLE 3. NAPSLP PIN SETTINGS NAPSLP PIN AVSS Float AVDD MODE Normal Sleep Nap
Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 33.
Gray Code
11
10
9
****
1
0
The power down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in "Serial Peripheral Interface" on page 18. This is an indexed function when controlled from the SPI, but a global function when driven from the pin.
****
Data Format
Output data can be presented in three formats: two's complement, Gray code and offset binary. The data format is selected via the OUTFMT pin as shown in Table 4.
TABLE 4. OUTFMT PIN SETTINGS OUTFMT PIN AVSS Float AVDD MODE Offset Binary Two's Complement Gray Code
****
Binary
11
10
9
****
1
0
FIGURE 33. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is shown in Table 5.
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
The data format can also be controlled through the SPI port, which overrides the OUTFMT pin setting. Details on this are contained in "Serial Peripheral Interface" on page 18. Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two's complement coding simply complements the MSB of the offset binary representation. When calculating Gray code the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 32 shows this operation.
INPUT VOLTAGE
OFFSET BINARY
TWO'S COMPLEMENT
GRAY CODE
-Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00 -Full Scale 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01 + 1LSB Mid-Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00 +Full Scale 111 11 111 11 10 011 11 111 11 10 100 00 000 00 01 - 1LSB +Full Scale 111 11 111 11 11 011 11 111 111 1 100 00 000 00 00
Binary
11
10
9
****
1
0
****
Gray Code 11 10 9 **** 1 0
FIGURE 32. BINARY TO GRAY CODE CONVERSION
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FN6803.0 December 5, 2008
KAD5612P
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 34. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 35. LSB-FIRST ADDRESSING
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data input (SDI), and serial data input/output (SDIO). The maximum SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 16 for write operations and fSAMPLE divided by 66 for reads. At fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and 3.79MHz for write operations. There is no minimum SCLK rate. The following sections describe various registers that are used to configure the SPI or adjust performance or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results.
The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in four-wire mode). If multiple slave devices are selected for reading at the same time, the results will be indeterminate. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high to low transition on CSB determines the beginning of the two-byte instruction/address command. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 34 and 35 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode the address is incremented for multi-byte transfers, while in LSB-first mode it's decremented. In the default mode the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read or written (see Table 6). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 36, and timing values are given in "Serial Peripheral Interface" on page 18. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the ADC (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin in three-wire mode. The state of the SDIO pin is set automatically in the communication protocol (described in the following paragraphs). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the KAD5612P functioning as a slave. Multiple slave devices can interface to a single master in four-wire mode only, since the SDIO output of an unaddressed device is asserted in three-wire mode.
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KAD5612P
tH
tS tDS
CSB
tCLK tHI tDH tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
FIGURE 36. INSTRUCTION/ADDRESS PHASE
CSB Stalling
CSB
SCLK
SDIO
Instruction/Address
Data Word 1
Data Word 2
FIGURE 37. 2-BYTE TRANSFER
Last Legal CSB Stalling
CSB
SCLK
SDIO
Instruction/Address
Data Word 1
Data Word N
FIGURE 38. N-BYTE TRANSFER
Bit 6 LSB First
TABLE 6. BYTE TRANSFER SELECTION [W1:W0] 00 01 10 11 BYTES TRANSFERRED 1 2 3 4 or more
Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset Setting this bit high resets all SPI registers to default values. Bit 4 Reserved This bit should always be set high. Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. ADDRESS 0X02: BURST_END
Figures 37 and 38 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various microcontrollers. Bit 7 SDO Active
If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. In 3-wire SPI mode the burst is ended by pulling the CSB pin high. If the device is operated in 2-wire mode the CSB pin is not available. In that case, setting the burst_end address determines the end of the transfer. During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses.
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Bits 7:0 Burst End Address This register value determines the ending address of the burst data. ADDRESS 0X22: GAIN_COARSE ADDRESS 0X23: GAIN_MEDIUM ADDRESS 0X24: GAIN_FINE Gain of each ADC core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
TABLE 8. COARSE GAIN ADJUSTMENT 0x22[3:0] 1100 1000 0100 0000 NOMINAL COARSE GAIN ADJUST (%) 4.2 2.8 1.4 0.0 -1.4 -2.8 -4.2
Device Information
ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION The generic die identifier and a revision number, respectively, can be read from these two registers.
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Intersil ADC products. Certain configuration commands (identified as Indexed in the SPI map) can be executed on a per-converter basis. This register determines which converter is being addressed for an Indexed command. It is important to note that only a single converter can be addressed at a time. This register defaults to 00h, indicating that no ADC is addressed. Error code `AD' is returned if any indexed register is read from without properly setting device_index_A. ADDRESS 0X20: OFFSET_COARSE ADDRESS 0X21: OFFSET_FINE The input offset of each ADC core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 7. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
TABLE 7. OFFSET ADJUSTMENTS 0x20[7:0] PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size COARSE OFFSET 255 -133LSB (-47mV) 0.0LSB (0.0mV) +133LSB (+47mV) 1.04LSB (0.37mV) 0x21[7:0] FINE OFFSET 255 -5LSB (-1.75mV) 0.0LSB +5LSB (+1.75mV) 0.04LSB (0.014mV)
0001 0010 0011
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS 0x23[7:0] PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size MEDIUM GAIN 256 -2% 0.00% +2% 0.016% 0x24[7:0] FINE GAIN 256 -0.20% 0.00% +0.2% 0.0016%
ADDRESS 0X25: MODES Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation, nap or sleep modes (refer to "Nap/Sleep" on page 16). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset.
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TABLE 10. POWER DOWN CONTROL 0x25[2:0] VALUE 000 001 010 100 POWER DOWN MODE Pin Control Normal Operation Nap Mode Sleep Mode
CLK/4 Slip Once CLK/4
4.00 ns
CLK = CLKP - CLKN CLK
1. 00 ns
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF The value in the skew_diff register adjusts the timing skew between the two ADCs cores. The nominal range and resolution of this adjustment are given in Table 11. The default value of this register after power-up is 00h.
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT 0x70[7:0] PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size DIFFERENTIAL SKEW 256 -6.5ps 0.0ps +6.5ps 51fs VALUE 000 001
CLK/4 Slip Twice
FIGURE 40. PHASE SLIP: CLK/4 MODE, fCLOCK = 1000MHz
ADDRESS 0X72: CLOCK_DIVIDE The KAD5612P has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to "Clock Input" on page 15). This functionality can be overridden and controlled through the SPI, as shown in Table 12. This register is not changed by a Soft Reset.
TABLE 12. CLOCK DIVIDER SELECTION 0x72[2:0] CLOCK DIVIDER Pin Control Divide by 1 Divide by 2 Divide by 4
ADDRESS 0X71: PHASE_SLIP When using the clock divider, it's not possible to determine the synchronization of the incoming and divided clock phases. This is particularly important when multiple ADCs are used in a time-interleaved system. The phase slip feature allows the rising edge of the divided clock to be advanced by one input clock cycle, as shown in Figures 39 and 40. This register is self-clearing.
CLK = CLKP - CLKN CLK
2.00 ns
010 100
ADDRESS 0X73: OUTPUT_MODE_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The KAD5612P can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin selects the mode and drive level (refer to "Digital Outputs" on page 16). This functionality can be overridden and controlled through the SPI, as shown in Table 13. Data can be coded in three possible formats: two's complement, Gray code or offset binary. By default, the tri-level OUTFMT pin selects the data format (refer to "Data Format" on page 17). This functionality can be overridden and controlled through the SPI, as shown in Table 14. This register is not changed by a Soft Reset.
CLK/2
4.00 ns
CLK/2 Slip Once
CLK/2 S lip Twice
FIGURE 39. PHASE SLIP: CLK/2 MODE, fCLOCK = 500MHz
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TABLE 13. OUTPUT MODE CONTROL OUTPUT MODE VALUE 000 001 010 100 0x93[7:5] Pin Control LVDS 2mA LVDS 3mA LVCMOS
Device Test
The KAD5612 can produce preset or user defined patterns on the digital outputs to facilitate in situ testing. A static word can be placed on the output bus, or two different words can alternate. In the alternate mode, the values defined as Word 1 and Word 2 (as shown in Table 16) are set on the output bus on alternating clock phases. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. The four LSBs in this register (Output Test Mode) determine the test pattern in combination with registers 0xC2 through 0xC5. Refer to Table 17.
TABLE 16. OUTPUT TEST MODES
TABLE 14. OUTPUT FORMAT CONTROL 0x93[2:0] VALUE 000 001 010 100 OUTPUT FORMAT Pin Control Two's Complement Gray Code Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B ADDRESS 0X75: CONFIG_STATUS Bit 6 DLL Range This bit sets the DLL operating range to fast (default) or slow. Internal clock signals are generated by a delay-locked loop (DLL), which has a finite operating range. Table 15 shows the allowable sample rate ranges for the slow and fast settings.
TABLE 15. DLL RANGES DLL RANGE Slow Fast MIN 40 80 MAX 100 fS MAX UNIT MSPS MSPS VALUE 0000 0001 0010 0011 0100 0101 0110 0111 1000
0xC0[3:0] OUTPUT TEST MODE Off Midscale Positive Full-Scale Negative Full-Scale Checkerboard Reserved Reserved One/Zero User Pattern 0x8000 0xFFFF 0x0000 0xAAAA N/A N/A 0xFFFF user_patt1 N/A N/A N/A 0x5555 N/A N/A 0x0000 user_patt2 WORD 1 WORD 2
ADDRESS 0XC2: USER_PATT1_LSB The output_mode_B and config_status registers are used in conjunction to select the frequency range of the DLL clock generator. The method of setting these options is different from the other registers.
Read output_mode_B 0x74 Read config_status 0x75 Desired Value
ADDRESS 0XC3: USER_PATT1_MSB These registers define the lower and upper eight bits, respectively, of the first user-defined test word. ADDRESS 0XC4: USER_PATT2_LSB ADDRESS 0XC5: USER_PATT2_MSB
Write to 0x74
These registers define the lower and upper eight bits, respectively, of the second user-defined test word.
FIGURE 41. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in Figure 41. Read the contents of output_mode_B and config_status and XOR them. Then XOR this result with the desired value for output_mode_B and write that XOR result to the register.
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SPI Memory Map
TABLE 17. SPI MEMORY MAP
Addr (Hex) 00 01 02 03-07 08 09 10 11-1F 20 21 22 23 24 25 Info SPI Config Parameter Name port_config reserved burst_end reserved chip_id chip_version device_index_A reserved offset_coarse offset_fine gain_coarse gain_medium gain_fine modes Bit 7 (MSB) SDO Active Bit 6 LSB First Bit 5 Soft Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # Reserved ADC01 Reserved Coarse Offset Fine Offset Medium Gain Fine Gain ADC00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Mirror (bit7) Def. Value Indexed/ (Hex) Global 00h 00h Read only Read only 00h cal. value cal. value cal. value cal. value cal. value 00h NOT affected by Soft Reset G G G G I I I I I I I
Mirror (bit5) Mirror (bit6)
Indexed Device Config/Control
Reserved
Coarse Gain
Power Down Mode [2:0] 000=Pin Control 001=Normal Operation 010=Nap 100=Sleep other codes=reserved
26-5F 60-6F 70 71 72 Global Device Config/Control
reserved reserved skew_diff phase_slip clock_divide
Reserved Reserved Different ial Skew Reserved Clock Divide [2:0] 000=Pin Control 001=divide by 1 010=divide by 2 100=divide by 4 other codes=reserved Output Format [2:0] 000=Pin Control 001=Twos Complement 010=Gray Code 100=Offset Binary other codes=reserved Next Clock Edge 80h 00h 00h NOT affected by Soft Reset G G G
73
output_mode_A
74
output_mode_B
Output Mode [2:0] 000=Pin Control 001=LVDS 2mA 010=LVDS 3mA 100=LVCMOS other codes=reserved DLL Range 0=fast 1=slow
00h NOT affected by Soft Reset
G
00h NOT affected by Soft Reset Read Only Reserved Reset PN Long Gen Reset PN Short Gen Output Test Mode [3:0] 0=Off 1=Midscale Short 2=+FS Short 3=- FS Short 4=Checker Board 5=reserved 6=reserved B2 B10 B2 B10 7=One/Zero Word Togg le 8=User Input 9-15=reserved 00h
G
75 76-BF C0
config_status reserved test _io
XOR Result User Test Mode [2:0] 00=Single 01=Alt ernate 10=Single Once 11=Alt ernate Once
G G
Device Test
C1 C2 C3 C4 C5 C6-FF
Reserved user_patt 1_lsb user_patt 1_msb user_patt 2_lsb user_patt 2_msb reserved
B7 B15 B7 B15
B6 B14 B6 B14
B5 B13 B5 B13
B4 B12 B4 B12
Reserved B3 B11 B3 B11 Reserved
B1 B9 B1 B9
B0 B8 B0 B8
00h 00h 00h 00h 00h
G G G G G
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FN6803.0 December 5, 2008
KAD5612P Equivalent Circuits
AVDD
AVDD
AVDD Csamp 1.6pF
To Clock-Phase Generation AVDD
11kO
INP F 2 F 3
To Charge Pipeline
CLKP
1000O
F1
18kO
Csamp 1.6pF
AVDD INN
To Charge Pipeline F 3
F1
2 F
AVDD
11kO
18kO
CLKN
FIGURE 42. ANALOG INPUTS
FIGURE 43. CLOCK INPUTS
AVDD AVDD
75kO
AVDD
AVDD AVDD
To Sense Logic
AVDD
75kO 280O
280O Input
Input
75kO
To Logic
75kO
FIGURE 44. TRI-LEVEL DIGITAL INPUTS
FIGURE 45. DIGITAL INPUTS
OVDD 2mA or 3mA OVDD DATA DATA D[11:0]P OVDD
D[11:0]N
OVDD OVDD
DATA
DATA
DATA
2mA or 3mA
D[11:0]
FIGURE 46. LVDS OUTPUTS
FIGURE 47. CMOS OUTPUTS
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KAD5612P Equivalent Circuits
(Continued)
AVDD
VCM 0.535V + -
FIGURE 48. VCM_OUT OUTPUT
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip.
floating if they are not used. Tri-level inputs (NAPSLP, OUTMODE, OUTFMT, CLKDIV) accept a floating input as a valid state, and therefore should be biased according to the desired functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD-1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less 2 LSB. It is typically expressed in percent. Integral Non-Linearity (INL) is the maximum deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N - 1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50 (100 differential) characteristic impedance. Keep traces direct and minimize bends where possible. Avoid crossing ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50 characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal ADC performance. These inputs can be left 25
FN6803.0 December 5, 2008
KAD5612P
Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the ADC FFT, caused by an AC signal superimposed on the power supply voltage. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter's full-scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic. Two-Tone SFDR is the ratio of the RMS value of the lowest power input tone to the RMS value of the peak spurious component, which may or may not be an IMD product.
Revision History
DATE 7/30/08 REVISION Rev 1 CHANGE Initial Release of Production Datasheet
12/5/08
Converted to intersil template. Assigned file number FN6803. Rev 0 - first release FN6803.0 with new file number.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 26
FN6803.0 December 5, 2008
KAD5612P
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08
10.00 PIN 1 INDEX AREA 6 54 A 4X 8.50 B 55 72 1
68X 0.50
PIN 1 INDEX AREA 6
10.00
Exp. DAP 6.00 Sq.
37 (4X) 0.15 36
TOP VIEW
18 72X 0.40
BOTTOM VIEW
19 72X 0.24
4
0.10 M C A B
0.90 Max
SEE DETAIL "X" C 0.10 C 0.08 C SEATING PLANE
SIDE VIEW
68X 0.50
9.80 Sq
72X 0.24
6.00 Sq
C
0 . 2 REF
5
72X 0.60
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
27
FN6803.0 December 5, 2008

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